This blog provides information/ideas about PCI Express Bus Protocol.
Monday, August 18, 2008
Tuesday, February 5, 2008
On the receive side of Physical Layer the incoming serial data from PCI Express link is converted into its original format such that parallel data and the added frames are removed and the packets are send back to Data Link Layer.
The Data Link Layer acts as an intermediate Layer between Transaction and Physical Layer, nothing but a Gate Keeper. The main responsibility of Data Link Layer is Error detection and correction.
Data Link Layer Model
Data Link Layer takes the TLP-Transaction Layer Packet from transmit side of the Transaction Layer. Here 12 bit sequence Number is added in front of the TLP and LCRC-Link CRC checker to the end.
Data Link Layer then forwards the applied TLP to the Physical Layer transmit side. On the receive side of Data Link Layer, accepts the packet from Physical Layer and checks the Sequence Number and LCRC with the applied Sequence Number and LCRC. If the Sequence Number/LCRC matches then the TLP are moved to receive side of Transaction Layer and generates ACK (Acknowledgement) signal. If there is any mismatches/error detects in Sequence Number or LCRC then Data Link Layer does not send the “Invalid or Bad” TLP to receive side of Transaction Layer, instead it generates NAK (Negative Acknowledgement). Data Link Layer now starts “Retry” attempts to send the valid TLP to Transaction Layer.
The Upper Layer of the architecture is the Transaction Layer. The main responsible of this layer is to begin the process of turning request or completion from device core into PCI Express transactions.
On the Transmit side, the transaction layer receives request or completion data from the core, and turns that information into out going PCI Express transaction.
On the Receive side the transaction layer accepts the incoming PCI Express transactions from its Data Link Layer.Transaction Layer Model
Transaction Layer uses TLP-Transaction Layer Packet to communicate request and complete data into other PCI Express devices. Each TLP has a Header to identify the type of transaction. The Transaction Layer request device generates the TLP and completion device consumes the TLP. Transaction Layer has several other operations which include “Flow Control” and “Power Management”.
Header identifies the information for the transaction (types). PCI Express architecture defines four transaction types.
· Memory Transaction
· I/O Transaction
· Configuration Transaction
· Message Transaction
Where as DLP and ECRC (End to End CRC) are optional.